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Automatic variables in Makefiles
Automatic variables in Makefiles
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Here is a simple demo showing the value of each automatic variable in a Makefile:
# Makefile using automatic variables
# http://www.gnu.org/software/make/manual/html_node/Automatic-Variables.html

CC = gcc
CFLAGS = -g -ansi -pedantic -Wall -O2

###TARGETS = kbd.o command.o files.o
TARGETS = main
PREREQUISITES            = command.h kbd.h dup.h nodup.h
PREREQUISITES_DUPLICATED = command.h kbd.h dup.h nodup.h dup.h

# Main target
.PHONY : $(TARGETS)
$(TARGETS): $(PREREQUISITES_DUPLICATED)
# $@ = target name
        @echo '$$@': This is the target: $@

# $% = target member name
ifeq ($(strip $($%)),)
        @echo '$$%': This target is not an archive member.
else
        @echo '$$%': This is the target member name, when the target is an archive member: $%
endif

# $< = first prerequisite
        @echo '$$<': This is the name of the first prerequisite: $<

# $? = prerequisite newer than target
ifeq ($(strip $($?)),)
        @echo '$$?': There are no prerequisites which are newer than the target.
else
        @echo '$$?': These are the prerequisites which are newer than the target: $?
endif

# $^ = prerequisites
        @echo '$$^': These are all the prerequisites: $^

# $+ = prerequisites, may be duplicated
        @echo '$$+': These are all the prerequisites, duplicates included: $+

# $| = All order-only prerequisites
ifeq ($(strip $($|)),)
        @echo '$$|': There are no order-only prerequisites.
else
        @echo '$$|': These are all the order-only prerequisites: $|
endif

# $* = The stem for an implicit rule
ifeq ($(strip $($*)),)
        @echo '$$*': This is an explicit rule without a suffix, so '$$*' is not set.
        @echo '   ' \(Don\'t worry, you should generally avoid using '$$*' anyway.\)
endif

# $(@D) = The directory part of the file name of the target
        @echo '$$(@D)': Target directory part: $(@D)
# $(@F) = The file-within-directory part of the file name of the target
        @echo '$$(@F)': Target file part: $(@F)

# Compile/link
        $(CC) $(CFLAGS) $@.c -o $@



# Prerequisites
# Manually: use 'make prereq'
.PHONY : prereq
prereq:
        touch $(PREREQUISITES)
# Automatically: '$(PREREQUISITES)' rule called by 'main' rule
$(PREREQUISITES):
        touch $(PREREQUISITES)

# Remove object files, executables (UNIX/Windows), Emacs backup files, and core files
.PHONY : clean
clean:
        rm -rf  *.o *.exe *~ *.core core
Read more about Automatic Variables in the GNU make manual.
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Last modified: Thu Sep 27 13:09:07 Romance Daylight Time 2007