Let's use the same C code as in the previous example.
We will only change the Makefile this time.
Using implicit rules means that we will let make guess the rules instead of explicitly writing them.
Let's have a look at the rule for the target world.o:
world.o: world.c world.h
cc -c world.c# TAB before command!
If the file world.c is found in the same directory as the Makefile, make can guess that you want to create the object file world.o with cc -c world.c.
As make can guess both the prerequisite (world.c) and the compiler command (cc -c world.c), these don't have to be explicitly written...
world.o: world.c world.h
cc -c world.c# TAB before command!
...but may be reduced to an implicit rule:
world.o: world.h
Applying this on the other rules in the Makefile reduces its size considerably:
OBJECTS = main.o printhelloworld.o hello.o world.o
# The executable 'helloworld' depends on all object files listed in $(OBJECTS)helloworld: $(OBJECTS)
cc -o helloworld $(OBJECTS)# TAB before command!# Implicit rulesmain.o:
printhelloworld.o: hello.h world.h
hello.o: hello.h
world.o: world.h
# Remove object files, executables (UNIX/Windows), Emacs backup files, and core files
.PHONY : clean
clean:
rm -rf $(OBJECTS) helloworld helloworld.exe *~ *.core core# TAB before command!
In this case, the implicit rules may even be omitted completely:
OBJECTS = main.o printhelloworld.o hello.o world.o
# The executable 'helloworld' depends on all object files listed in $(OBJECTS)helloworld: $(OBJECTS)
cc -o helloworld $(OBJECTS)# TAB before command!# Remove object files, executables (UNIX/Windows), Emacs backup files, and core files
.PHONY : clean
clean:
rm -rf $(OBJECTS) helloworld helloworld.exe *~ *.core core# TAB before command!
An extreme example of implicit rules is to use make in a directory with only .c files, but without any Makefile!
Let's say you have the following files: prog1.c, prog2.c, prog3.c...,
Now you can type
make prog1
make prog2
make prog3
...
as long as the target matches an existing C source code file name (without the .c extension). make prog1 will find prog1.c and build the target with cc prog1.c -o prog1.
Anyway, while it may be a quick way to try out programs without creating a Makefile, it is not recommended in the long run, as neither make nor make clean will work due to the missing Makefile.
